1. Field of the Invention
The invention relates to the field of semiconductor processing and more particularly to the process of doping the substrate of a CMOS integrated circuit.
2. Description of the Relevant Art
In complimentary metal-oxide-semiconductor (CMOS) integrated circuits, in which n-channel and p-channel transistors are fabricated in a single semiconductor substrate, threshold voltage and drain current are controlled through a number of interrelated process steps. The resistivity of the starting material and the subsequent doping of the starting material result in a substrate doping profile that, together with the thickness of the gate oxide, the quantity of charged sites within the gate oxide, and other variables, determine the threshold voltage and other critical operating parameters of the integrated circuit.
In a twin-well CMOS process, an n-well and a p-well are formed in the substrate with an n-type and a p-type dopant respectively. Early twin-well processes used two masking steps to form the wells. One of the masking steps prevented the n-type dopant from entering the p-well during formation of the n-well while the other masking step prevented the p-type dopant from entering the n-well during the formation of the p-well. A single-mask well formation process was developed to reduce the demands on expensive photolithography equipment. In such a process, the single masking step is used to pattern a silicon nitride layer on the semiconductor surface to expose the first well region. After the first well dopant is introduced into the first well region, a thermal oxidation is performed to grow a "well oxide" over the first well region while the nitride film prevents the growth of a significant oxide film over the second well region. The well oxide serves as a blocking layer over the first well region. The nitride film is thereafter removed, the second dopant introduced into the second well region, and, finally, the well oxide is stripped from the wafer. See, e.g., 2 S. Wolf, Silicon Processing for the VLSI Era, 432-33 (Lattice Press 1990) [hereinafter Wolf]. Despite eliminating a masking step, the single mask process described results in a non-planar substrate upper surface because the well oxidation process consumes a portion of the substrate in the first well region of the substrate thereby creating a "step" at the interface of the n-well and p-well regions. Non-planar surfaces increase the complexity of subsequent processing steps, including the patterning and etching of fine line interconnects. Such interconnects tend to undesirably "notch" over steps in the underlying topography creating localized regions of potentially high current density and, consequently, reduced reliability. See, e.g., 1 Wolf at 437-41 (Lattice Press 1986).
After the formation of the wells, the substrate is further selectively doped to minimize punchthrough subthreshold currents, increase the channel stop doping, and to adjust the threshold voltages to desirable levels. Each of these steps may require its own pair of masking steps and, accordingly, may still further increase the demands on the photolithography equipment. The two-mask threshold adjust process cannot typically be circumvented with a nitride mask/ thermal oxidation substitute as described above because the high temperature oxidation cycle would undesirably drive the first threshold impurity into the substrate away from the substrate upper surface. Thus, a conventional substrate doping sequence in a twin-well CMOS process includes a minimum of three masking steps and results in a non-planar step at the interface of the two well regions. It would be highly desirable to implement a process for doping the substrate of a semiconductor device requiring a single masking step and producing a substantially planar substrate upper surface.